Complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuit design has been an ever-lasting research field. It has gained so much attention since RF circuits offer high mobility and wide-band efficiency, while CMOS technology provides the advantage of low cost and high integration capability. At the same time, CMOS device size continues to scale to the nanometer regime. Reliability issues with RF circuits have become more challenging than ever before. Reliability mechanisms, such as gate oxide breakdown, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. In addition, process variability becomes a new design paradigm in modern RF circuits. In this Ph.D. work, a class F power amplifier (PA) was designed and analyzed using TSMC 180nm process technology. Its pre-layout and post-layout performances were compared. Post-layout parasitic effect decreases the output power and power-added efficiency. Physical insight of hot electron impact ionization and device self-heating was examined using the mixed-mode device and circuit simulation to mimic the circuit operating environment. Hot electron effect increases the threshold voltage and decreases the electron mobility of an n-channel transistor, which in turn decreases the output power and power-added efficiency of the power amplifier, as evidenced by the RF circuit simulation results. The device self-heating also reduces the output power and power-added efficiency of the PA. The process, voltage, and temperature (PVT) effects on a class AB power amplifier were studied. A PVT compensation technique using a current-source as an on-chip sensor was developed. The adaptive body bias design with the current sensing technique makes the output power and power-added efficiency much less sensitive to process variability, supply voltage variation, and temperature fluctuation, predicted by our derived analytical equations which are also verified by Agilent Advanced Design System (ADS) circuit simulation. Process variations and hot electron reliability on the mixer performance were also evaluated using different process corner models. The conversion gain and noise figure were modeled using analytical equations, supported by ADS circuit simulation results. A process invariant current source circuit was developed to eliminate process variation effect on circuit performance. Our conversion gain, noise figure, and output power show robust performance against PVT variations compared to those of a traditional design without using the current sensor, as evidenced by Monte Carlo statistical simulation. Finally, semiconductor process variations and hot electron reliability on the LC-voltage controlled oscillator (VCO) performance was evaluated using different process models. In our newly designed VCO, the phase noise and power consumptions are resilient against process variation effect due to the use of on-chip current sensing and compensation. Our Monte-Carlo simulation and analysis demonstrate that the standard deviation of phase noise in the new VCO design reduces about five times than that of the conventional design.
Doctor of Philosophy (Ph.D.)
College of Engineering and Computer Science
Electrical Engineering and Computer Engineering
Length of Campus-only Access
Doctoral Dissertation (Open Access)
Kritchanchai, Ekavut, "RF Circuit Designs for Reliability and Process Variability Resilience" (2016). Electronic Theses and Dissertations. 4903.