Electrostatic Discharges (ESD) are one of the main reliability threats in modern electronics. Design, implementation, and characterization of ESD and transient protection of these modern electronics are increasingly challenging due to the process, packaging and cost constraints. Growing communication between ‘objects’ to be sensed and controlled remotely is creating opportunities for greater integration with computer systems, resulting in improved efficiency, accuracy and economic benefits across existing and emerging network infrastructures. This tendency is driving an expansion in data communication as well as industrial applications environment. To keep up with the interconnectivity expansion, the industry requires new devices to support more effectively high speed signals processing over long distances and be able to reliably operate in harsh and noisy environments. Electrical over-stress transients caused by ESD or switching of inductive loads can corrupt data transmission and damage bus transceivers unless effective measures are taken to address the impact of such high energy transient stress conditions. Today’s industry specifications for integrated circuits require 1kV HBM on all pins, but selected pins with direct contact to the external environment must comply with levels as high as 8kV for IEC 61000-4-2 and ISO 10605 standards. The rapid evolution of the handheld and mobile device market segment, dramatic increase of electronic content in automotive products, and substantial progress in industrial and medical applications created a new need for on-chip protection against system level ESD stresses. This PhD work investigates the impact of system-level type of ESD stress on components. Firstly, correlation factors between different ESD pulse types for different BEOL metal line topologies have been studied to support system level on-chip ESD design. The component level (HMM, HBM and TLP on wafer) and system level (IEC gun contact on package) ESD stresses were correlated followed by extraction of correlation factors between the IEC/HMM and TLP, as well as the HBM and TLP supported by analytical approximation. The major conclusions were verified using the thermal coupled mixed-mode simulations analysis. Secondly, operation of NLDMOS-SCR devices under the HMM and IEC air gap electrostatic discharge (ESD) stresses has been studied based on both the pulsed measurements and mixed-mode simulations. Under the IEC air gap testing, the devices are found to suffer the non-uniform multi-finger turn-on behavior and hence a relatively low passing level, while both the IEC contact and HMM stresses do not give rise to such an adversary effect and result in a considerably higher passing level. It is further shown that the non-uniform multi-finger turn-on effect depends on the stress pulse rise time. Such a dependency has also been examined and verified using the transmission line pulsing (TLP) technique with rise times ranging from 10 to 40ns. In the last section, a new silicon-controlled rectifier (SCR) fabricated in a 30 V mixedsignal CDMOS (CMOS/DMOS) technology is presented. This device allows for robust EMI (electromagnetic interference) and ESD (electrostatic discharge) protection solution for high speed industrial interface applications operating in variable voltage swing range from -7V to +12V. This new SCR has reduced overshoot voltage and leakage current when electrically stressed under different pulse widths and temperatures. Analysis of the device physics is complemented via numerical TCAD mixed-mode simulations. A 200 x 200 µm2 device designed in an annular configuration achieved > ± 8 kV IEC robustness by handling > ± 20 Amp of TLP current while clamping the voltage to ±3V within 2-nsec.


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Graduation Date





Liou, Juin


Doctor of Philosophy (Ph.D.)


College of Engineering and Computer Science


Electrical Engineering and Computer Engineering

Degree Program

Electrical Engineering









Release Date

May 2021

Length of Campus-only Access

5 years

Access Status

Doctoral Dissertation (Campus-only Access)