Testing The Impact Of Process Defects On Ecl Power-Delay Performance
Abbreviated Journal Title
Int. J. Electron.
BIPOLAR-TRANSISTORS; CAPACITANCE; Engineering, Electrical & Electronic
The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evaluated. We have developed modelling equations including process defects in the delay analysis. The delay equation provides an insight into the sensitivity of various process defects on the ECL gate delay. The testing model equations are physics-based and can be generalized to digital circuits other than ECL.
International Journal of Electronics
"Testing The Impact Of Process Defects On Ecl Power-Delay Performance" (1993). Faculty Bibliography 1990s. 961.