Testing The Impact Of Process Defects On Ecl Power-Delay Performance

    Authors

    J. S. Yuan

    Comments

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    Abbreviated Journal Title

    Int. J. Electron.

    Keywords

    BIPOLAR-TRANSISTORS; CAPACITANCE; Engineering, Electrical & Electronic

    Abstract

    The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evaluated. We have developed modelling equations including process defects in the delay analysis. The delay equation provides an insight into the sensitivity of various process defects on the ECL gate delay. The testing model equations are physics-based and can be generalized to digital circuits other than ECL.

    Journal Title

    International Journal of Electronics

    Volume

    74

    Issue/Number

    2

    Publication Date

    1-1-1993

    Document Type

    Article

    Language

    English

    First Page

    201

    Last Page

    207

    WOS Identifier

    WOS:A1993KQ79800003

    ISSN

    0020-7217

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