A spice-like reliability model for deep-submicron CMOS technology
Abbreviated Journal Title
MOS devices; reliability; hot-carrier stress; MOSFETS; DEGRADATION; DAMAGE; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter
Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and good agreements between the measured and simulated results have been obtained for devices fabricated from the 0.18-mu m CMOS technology. (c) 2005 Elsevier Ltd. All rights reserved.
"A spice-like reliability model for deep-submicron CMOS technology" (2005). Faculty Bibliography 2000s. 5101.