Title

A spice-like reliability model for deep-submicron CMOS technology

Authors

Authors

Z. Cui;J. J. Liou

Comments

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Abbreviated Journal Title

Solid-State Electron.

Keywords

MOS devices; reliability; hot-carrier stress; MOSFETS; DEGRADATION; DAMAGE; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter

Abstract

Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and good agreements between the measured and simulated results have been obtained for devices fabricated from the 0.18-mu m CMOS technology. (c) 2005 Elsevier Ltd. All rights reserved.

Journal Title

Solid-State Electronics

Volume

49

Issue/Number

10

Publication Date

1-1-2005

Document Type

Article

Language

English

First Page

1702

Last Page

1707

WOS Identifier

WOS:000233750300021

ISSN

0038-1101

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