Keywords

Multiprocessors -- Computer simulation

Abstract

A simulation of an alternate implementation of a redundant busing network based on the Teradata Ynet architecture is presented. An overview of the Teradata DBC/1012 data base parallel processing computer including the Ynet, an active logic busing network, is given. Other multiprocessor busing networks are examined and compared to the standard Ynet and the alternate Ynet.

In the standard Ynet system, two networks, called Ynets, process message packets concurrently. When one of the Ynet paths fails, the system is reset. The remaining Ynet path restarts using the previously interrupted packets and processing continues without the aid of the failed Ynet. In the implementation presented here, the two busing networks process the message packets in parallel. Now, when one of the Ynet paths fails, the other continues processing the packets without interruption. This implementation can be referred to as a parallel Ynet.

The advantages and disadvantages of the parallel Ynet are discussed and suggestions for further research are given. Listings and sample outputs are included in the appendices.

Notes

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Graduation Date

1987

Semester

Fall

Advisor

Myler, Harley R.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Computer Engineering

Format

PDF

Pages

194 p.

Language

English

Rights

Public Domain

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0020530

Accessibility Status

Searchable text

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