Array Noise-Analysis For Multimegabit Dram Design

    Authors

    J. S. Yuan;J. J. Liou

    Comments

    Authors: contact us about adding a copy of your work at STARS@ucf.edu

    Abbreviated Journal Title

    Int. J. Electron.

    Keywords

    Engineering, Electrical & Electronic

    Abstract

    An analytical model for bit-line coupling noise in various DRAM architectures has been developed. The analytical expressions developed provide insight into the charge redistribution when the word lines turn on. They are also useful for determining the noise-to-signal ratio and for designing the sense amplifier circuit. Noise extracted from SPICE circuit simulation is included and is compared against the results from the present analytical model. Good agreement is found.

    Journal Title

    International Journal of Electronics

    Volume

    74

    Issue/Number

    2

    Publication Date

    1-1-1993

    Document Type

    Article

    Language

    English

    First Page

    265

    Last Page

    279

    WOS Identifier

    WOS:A1993KQ79800010

    ISSN

    0020-7217

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