Delay-insensitive gate-level pipelining

    Authors

    S. C. Smith; R. F. DeMara; J. S. Yuan; M. Hagedorn;D. Ferguson

    Comments

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    Abbreviated Journal Title

    Integration-VLSI J.

    Keywords

    asynchronous logic design; self-timed circuits; dual-rail encoding; pipelining; NULL convention logic (NCL); CIRCUITS; Computer Science, Hardware & Architecture; Engineering, Electrical &; Electronic

    Abstract

    Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit x 4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity. (C) 2001 Elsevier Science B.V. All rights reserved.

    Journal Title

    Integration-the Vlsi Journal

    Volume

    30

    Issue/Number

    2

    Publication Date

    1-1-2001

    Document Type

    Article

    Language

    English

    First Page

    103

    Last Page

    131

    WOS Identifier

    WOS:000172016100001

    ISSN

    0167-9260

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