Title

Modeling of mismatch effect in submicron MOSFETs based on BSIM3 model and parametric tests

Authors

Authors

Q. Zhang; J. J. Liou; J. McMacken; J. Thomson;P. Layman

Comments

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Abbreviated Journal Title

IEEE Electron Device Lett.

Keywords

analog circuits; BSIM3v3 model; modeling; MOS transistor mismatch; MOS-TRANSISTORS; Engineering, Electrical & Electronic

Abstract

Mismatch between identically designed MOS transistors plays an important role in the performance of analog circuits. This paper reports a MOS transistor mismatch model applicable for submicron CMOS technology and developed based on the industry standard BSIM3v3 model. A quick way to estimate drain current mismatch based on parametric test data was also suggested.

Journal Title

Ieee Electron Device Letters

Volume

22

Issue/Number

3

Publication Date

1-1-2001

Document Type

Article

Language

English

First Page

133

Last Page

135

WOS Identifier

WOS:000167324700009

ISSN

0741-3106

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