Worst-case analysis and statistical simulation of MOSFET devices based on parametric test data

    Authors

    Q. Zhang; J. J. Liou; J. McMacken; J. R. Thomson; K. Stiles;P. Layman

    Comments

    Authors: contact us about adding a copy of your work at STARS@ucf.edu

    Abbreviated Journal Title

    Solid-State Electron.

    Keywords

    worst-case analysis; statistical simulation; parametric test data; BSIM3v3 model; principal component analysis; Latin hypercube sampling; MOSFET devices; digital circuits; VLSI; METHODOLOGY; CIRCUITS; MODELS; Engineering, Electrical & Electronic; Physics, Applied; Physics, ; Condensed Matter

    Abstract

    A practical and efficient approach for estimating the MOSFET device and circuit performance distributions is presented. The proposed method is based on the Latin hypercube sampling technique and direct extracting and utilizing the statistical information obtained from a population of parametric test data. Using this approach, a set of worst-case models taking into account data correlations and equal probability constraints is developed. The procedure allows for a systematical and accurate way to predict the performance spread and worst case of MOSFET circuits, as well as a greatly reduced computation time for statistical simulation. Measured data of two digital circuits are included in support of the modeling work. (C) 2001 Elsevier Science Ltd. All rights reserved.

    Journal Title

    Solid-State Electronics

    Volume

    45

    Issue/Number

    9

    Publication Date

    1-1-2001

    Document Type

    Article

    Language

    English

    First Page

    1537

    Last Page

    1547

    WOS Identifier

    WOS:000171362300004

    ISSN

    0038-1101

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