Energy-efficient self-timed circuit design using supply voltage scaling

    Authors

    W. Kuang;J. S. Yuan

    Comments

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    Abbreviated Journal Title

    IEE Proc.-Circuit Device Syst.

    Keywords

    LOW-POWER; OPTIMIZATION; Engineering, Electrical & Electronic

    Abstract

    Energy-efficient design for self-timed circuits is investigated. Null convention logic is employed to construct speed-independent self-timed circuits. For error-free computation, the supply voltage automatically tracks the input data rate so that the supply voltage can be kept as small as possible while maintaining the speed requirement. For error-tolerable computation, such as soft digital signal processing, further energy saving is achieved at the cost of signal-to-noise ratio when an ultralow supply voltage is applied. Cadence simulation shows that 40 to 70% power can be saved by introducing -15 to -11 dB error in typical speech signal processing.

    Journal Title

    Iee Proceedings-Circuits Devices and Systems

    Volume

    151

    Issue/Number

    4

    Publication Date

    1-1-2004

    Document Type

    Article

    Language

    English

    First Page

    278

    Last Page

    284

    WOS Identifier

    WOS:000224250100002

    ISSN

    1350-2409

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