Design and Implementation of Three-Phase Two-Stage Grid-Connected Module Integrated Converter

    Authors

    L. Chen; A. Amirahmadi; Q. Zhang; N. Kutkut;I. Batarseh

    Comments

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    Abbreviated Journal Title

    IEEE Trans. Power Electron.

    Keywords

    Center points iteration (CPI); maximum power point tracking (MPPT); module integrated converter (MIC); three phase; two stage; PV SYSTEMS; INVERTER; MICROINVERTER; CAPACITORS; Engineering, Electrical & Electronic

    Abstract

    Module integrated converters (MICs) in single phase have witnessed recent market success due to unique features such as improved energy harvest, improved system efficiency, lower installation costs, plug-and-play operation, and enhanced flexibility and modularity. The MIC sector has grown from a niche market to mainstream, especially in the United States. Assuming further expansion of the MIC market, this paper presents the microinverter concept incorporated in large size photovoltaic (PV) installations such as megawatts (MW)-class solar farms where a three-phase ac connection is employed. A high-efficiency three-phase MIC with two-stage zero voltage switching (ZVS) operation for the grid-tied PV system is proposed which will reduce cost per watt, improve reliability, and increase scalability of MW-class solar farms through the development of new solar farm system architectures. The first stage consists of a high-efficiency full-bridge LLC resonant dc-dc converter which interfaces to the PV panel and produces a dc-link voltage. A center points iteration algorithm developed specifically for LLC resonant topologies is used to track the maximum power point of the PV panel. The second stage is comprised of a three-phase dc-ac inverter circuit which employs a simple soft-switching scheme without adding auxiliary components. The modeling and control strategy of this three-phase dc-ac inverter is described. Because the dc-link capacitor plays such an important role for dual-stage MIC, the capacitance calculation is given under type D voltage dip conditions. A 400-W prototype was built and tested. The overall peak efficiency of the prototype was measured and found to be 96% with 98.2% in the first stage and 98.3% in the second stage.

    Journal Title

    Ieee Transactions on Power Electronics

    Volume

    29

    Issue/Number

    8

    Publication Date

    1-1-2014

    Document Type

    Article

    Language

    English

    First Page

    3881

    Last Page

    3892

    WOS Identifier

    WOS:000334117900004

    ISSN

    0885-8993

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