Compact failure modeling for devices subject to electrostatic discharge stresses - A review pertinent to CMOS reliability simulation

    Authors

    M. Miao; Y. Z. Zhou; J. A. Salcedo; J. J. Hajjar;J. J. Liou

    Comments

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    Abbreviated Journal Title

    Microelectron. Reliab.

    Keywords

    Electrostatic discharge (ESD); Gate oxide breakdown; Junction thermal; failure; Thermal network; Transmission line pulsing (TLP); Transient; power law (TPL); GATE OXIDE BREAKDOWN; SEMICONDUCTOR-DEVICES; SILICON DIOXIDE; ESD; TRANSISTORS; STATISTICS; PROTECTION; PULSE; Engineering, Electrical & Electronic; Nanoscience & Nanotechnology; Physics, Applied

    Abstract

    This paper reviews the physical mechanisms and compact modeling approaches of two physical damages in MOS devices induced by electrostatic discharge (ESD) stresses; namely gate oxide breakdown and thermal failures. Theories underlying the failure mechanism are discussed and compact models that can be used to monitor ESD induced gate oxide breakdown and thermal failure are developed. Related work reported in the literature is discussed, and benchmarking of measurement data versus simulation results are included in support of the modeling work. (C) 2014 Elsevier Ltd. All rights reserved.

    Journal Title

    Microelectronics Reliability

    Volume

    55

    Issue/Number

    1

    Publication Date

    1-1-2015

    Document Type

    Review

    Language

    English

    First Page

    15

    Last Page

    23

    WOS Identifier

    WOS:000348957600002

    ISSN

    0026-2714

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