Abstract

Window functions have been greatly utilized in the synthesis of finite impulse response (FIR) filters implemented using surface acoustic wave (SAW) devices. The critical parameter in any FIR design in the impulse response length, which must be optimized for the given design specifications in order to reduce the size of each device. To this end, many design algorithms have been introduced such as Remez exchange, linear programming, and least mean squares. A new algorithm has been derived which is efficient and accurate for the design of arbitrary filter specifications requiring less computations than the current algorithms. The FIR design is applicable to general SAW filter design and allows two weighted transducers to be designed in a near optimal method without the need to perform zero splitting of de-convolution. The thesis first provides the definition of the window functions used for the design process. Then the overview of the design process is discussed using a flowchart of the modeling program for designing and FIR without transducer separation and sample simulation is presented. Next, the effects of monotonically increasing sidelobes on the transition bandwidth are discussed. This is followed by a discussion of the addition of arbitrary phase to the filter design requirements. Next, the separation of the response into a two transducer design utilizing the two window function series is explained. Finally, the results are discussed and compared with other design techniques.

Graduation Date

1995

Semester

Spring

Advisor

Malocha, Donald C.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Electrical and Computer Engineering

Degree Program

Electrical Engineering

Format

PDF

Language

English

Rights

Written permission granted by copyright holder to the University of Central Florida Libraries to digitize and distribute for nonprofit, educational purposes.

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0000186

Accessibility Status

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