An event-driven hierarchical structural level simulator

Abstract

An event-driven, hierarchical, configurable, structural level simulator is designed to support instruction in logic level design and also research in si1nulator design and implementation. The Structural Level Simulator (SLS) includes the primitive operators AND, OR, INVERT, and D-LATCH. It provides for hierarchical descriptions of logic circuits in a design library environment. A preprocessor 1nerges descriptions in the design library for simulation. The simulation is event-driven and supports tin1ing level analysis at the gate level.

Notes

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Graduation Date

1991

Semester

Fall

Advisor

Petrasko, Brian E.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Computer Engineering

Degree Program

Computer Systems

Format

PDF

Pages

95 p.

Language

English

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0029058

Subjects

Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic

Accessibility Status

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