A Time Delay and Integration Design for Focal Plane Arrays

Abstract

This thesis presents a design concept for the implementation of a focal plane array (FPA) time division multiplexer (TOM) which uses time delay integration (TOI) to minimize fixed pattern noise arising from capacitor tolerances. This is accomplished by using a serial TDI architecture as opposed to the more traditional parallel structures. In addition, scan line fixed pattern noise is reduced by using a programmable array multiplying digital-to-analog converter (MDAC) which operates from an on-plane random access memory. The FPA multiplexer used here may be described as follows. The input stage is a standard buffered injection (BI) amplifier configuration coupled with the photovoltaic detector. The FPA multiplexer performs the TOI in a serial manner with one sample per detector angular subtense (DAS). The FPA has four bits of gain enhanced resolution to provide uniformity correction. The output multiplexer buffer is designed to transfer the data off-plane to the external processing electronics while conserving power consumption across the plane. The methodology and rational behind each stage design is discussed and simulated using MICRO-CAP II circuit analysis program.

Notes

This item is only available in print in the UCF Libraries. If this is your thesis or dissertation, you can help us make it available online for use by researchers around the world by STARS for more information.

Graduation Date

1989

Semester

Fall

Advisor

Miller, Richard N.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Electrical Engineering and Communication Sciences

Format

PDF

Pages

85 p.

Language

English

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0026650

Subjects

Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic

Accessibility Status

Searchable text

This document is currently not available here.

Share

COinS