Timing Margin Examination Using Laser Probing Technique
A laser probing procedure has been developed to examine the timing margin of signal paths in complex CMOS devices. In the procedure, injected current at one of the logic gate's transistor drains increases the propagation delay of the logic gate. This occurs because increased current at the transistor drain decreases the rate of charge transfer between the logic gate and its output load. Using an indirect measurement scheme, a curve depicting laser induced propagation delay as a function of illumination is experimentally generated. This curve is then analyzed to determine whether or not the examined signal path has critical timing. This indirect measurement technique is verified by using simulation techniques.
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Brown, Harold K.
Master of Science (M.S.)
College of Engineering
Electrical Engineering and Communication Sciences
Length of Campus-only Access
Masters Thesis (Open Access)
Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic
Fuller, Glenn Curtis, "Timing Margin Examination Using Laser Probing Technique" (1989). Retrospective Theses and Dissertations. 4137.