An Adaptive Dataflow Scheduler for an N-Processor Architecture

Abstract

The problem of scheduling software tasks for execution in a Multiple Instruction, Multiple Data (MIMD) computer system architecture, such as that used in aircraft flight simulation, is addressed. Of the standard scheduling approaches discussed, the method employing a combination of synchronous (repetitive) and asynchronous (event-driven) techniques is the most widely used, but requires the system designer to manually determine the execution order of the tasks. When this manual process is applied to a system containing several processors (as found in an MIMD architecture) and hundreds of tasks (as found in aircraft simulation) the system designer is faced with a large number of possible combinations of processors and tasks. This makes it difficult to effectively arrange the task execution sequence. As an alternative to the manual scheduling process, a dataflow scheduler is presented. The dataflow scheduler automatically maximizes processor utilization across the MIMD architecture, and ensures that the set of tasks in the system is executed in the correct order given by the flow of data from task to task. The scheduler correctly handles synchronous and asynchronous tasks, giving priority to synchronous tasks, while fairly executing asynchronous tasks. The asynchronous task fairness allows new data to enter the simulation even if the current set of synchronous tasks occupy the entire simulation frame.

Notes

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Graduation Date

1989

Semester

Spring

Advisor

Linton, Darrell G.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Computer Engineering

Format

PDF

Pages

188 p.

Language

English

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0027044

Subjects

Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic

Accessibility Status

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