VLSI Implementation of a Configurable Neural Node

Abstract

A compact neural network architecture using a hybrid digital-analog design is implemented in Very Large Scale Integration (VLSI). Various ways to implement an efficient and practical neural node in electronic hardware are examined. Digital, analog and a combination of these methods are evaluated as a means of implemention. Design examples of these methods using VLSI are presented and the advantages and disadvantages are discussed. The network architecture presented uses VLSI to alleviate some of the interconnectivity problems involved with current neural network implementations. The resulting chip can be used to perform simulations in real time of different learning algorithms and to build large systems of neural nodes. The different node models were designed and tested using VLSI computer Aided Design (CAD) tools. A complete network was then constructed in VLSI using the most efficient and practical node model.

Notes

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Graduation Date

1989

Semester

Summer

Advisor

Myler, Harley R.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Computer Engineering

Format

PDF

Pages

86 p.

Language

English

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0027224

Subjects

Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic

Accessibility Status

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