VLSI Implementation of a Configurable Neural Node
A compact neural network architecture using a hybrid digital-analog design is implemented in Very Large Scale Integration (VLSI). Various ways to implement an efficient and practical neural node in electronic hardware are examined. Digital, analog and a combination of these methods are evaluated as a means of implemention. Design examples of these methods using VLSI are presented and the advantages and disadvantages are discussed. The network architecture presented uses VLSI to alleviate some of the interconnectivity problems involved with current neural network implementations. The resulting chip can be used to perform simulations in real time of different learning algorithms and to build large systems of neural nodes. The different node models were designed and tested using VLSI computer Aided Design (CAD) tools. A complete network was then constructed in VLSI using the most efficient and practical node model.
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Myler, Harley R.
Master of Science (M.S.)
College of Engineering
Length of Campus-only Access
Masters Thesis (Open Access)
Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic
Winter, Mitchell Alan, "VLSI Implementation of a Configurable Neural Node" (1989). Retrospective Theses and Dissertations. 4248.