Abstract
A gate array is a semi-custom designed integrated circuit. The integrated circuit is designed by a customer and then turned over to a vendor to be manufactured. A single gate array is capable of replacing a full board or more of SSI and MSI components. An area calculation path of a special purpose computer that was designed into a gate array. LSI Logic Corporation was used as the vendor. The gate array was designed and then simulated with the Tegas Description Language. The simulation revealed a worst case timing problem which was corrected by adding an additional stage in the pipeline. The additional stage increased the time a first result is available at the output of the pipeline, but did not effect the rate at which successive results are available. The simulation and actual gate array prototype were proven with a calculated set of test vectors. The benefit of using gate arrays comes from reduced costs and increased reliability
Notes
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Graduation Date
1986
Semester
Summer
Advisor
Petrasko, Brian E.
Degree
Master of Science (M.S.)
College
College of Engineering
Format
Pages
48 p.
Language
English
Rights
Public Domain
Length of Campus-only Access
None
Access Status
Masters Thesis (Open Access)
Identifier
DP0020383
STARS Citation
Janssen, Edward J., "The Gate Array Implementation of an Area Calculation Pipeline" (1986). Retrospective Theses and Dissertations. 4973.
https://stars.library.ucf.edu/rtd/4973
Contributor (Linked data)
University of Central Florida. College of Engineering [VIAF]
Accessibility Status
Searchable text