Abstract
This report discusses high speed latchup-free 0.5 µ m-channel CMOS using self-aligned TiSi2 and deep-trench isolation n-well technology. This technology of deep-trench isolation combined with the epitaxial layer eliminates many problems such as poor device to device isolation, latchup susceptibility and relatively high sheet resistance of n+ and p+ diffusion layers. Thus CMOS devices operate at a propagation delay time of 140 p with a power dissipation of 1.5mW per inverter and attain a maximum clock frequency of 700 MHZ without suffering from latchup even at a latchup trigger current of 100 mA.
Notes
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Graduation Date
1986
Semester
Fall
Advisor
Malocha, Donald C.
Degree
Master of Science (M.S.)
College
College of Engineering
Format
Pages
40 p.
Language
English
Rights
Public Domain
Length of Campus-only Access
None
Access Status
Masters Thesis (Open Access)
Identifier
DP0020385
STARS Citation
Mohamedi, Faheem, "High Speed Latchup-Free CMOS Using TiSi2, N-Well, Technology" (1986). Retrospective Theses and Dissertations. 4975.
https://stars.library.ucf.edu/rtd/4975
Contributor (Linked data)
University of Central Florida. College of Engineering [VIAF]
Accessibility Status
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