Abstract
A gain enhanced common gate transresistance circuit is typically used as the coupling circuit between detector and multiplexer in a focal plane array. At an operating temperature of 77 degrees Kelvin, the dominant noises in the system are shot noise and 1/f noise. The 1/f noise corner frequency of the CMOS amplifiers used in focal plane arrays can .be as high as 10 kHz. In this paper it is shown that the 1/f noise corner frequency contributed to the system noise by the amplifier is a function of the bias voltage applied to the photodiode detector. Specifically, as the reverse bias to the detector increases, the 1/f noise corner contributed to the system by the amplifier decreases, while the 1/f noise corner contributed to the system by the photodiode increases. This implies there is a trade off between the amplifier contributed 1/f noise corner and the photodiode contributed 1/f noise corner. Therefore there is an optimum bias voltage, which is not zero volts, where the overall noise in the system will be at a minimum.
Notes
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Graduation Date
1987
Semester
Fall
Advisor
Martin, Robert J.
Degree
Master of Science (M.S.)
College
College of Engineering
Format
Pages
84 p.
Language
English
Rights
Public Domain
Length of Campus-only Access
None
Access Status
Masters Thesis (Open Access)
Location
Orlando (Main) Campus
Identifier
DP0025745
STARS Citation
Reiff, Kirk B., "Bias Optimization for Noise Reduction in Focal Plane Arrays" (1987). Retrospective Theses and Dissertations. 5083.
https://stars.library.ucf.edu/rtd/5083
Accessibility Status
Searchable text