Keywords
Asynchronous circuits, Electric power Conservation
Abstract
Power dissipation has become a major concern for IC designers. Various low power design techniques have been developed for synchronous circuits. Asynchronous circuits, however. have gained more interests recently due to their benefits in lower noise, easy timing control, etc. But few publications on energy reduction techniques for asynchronous logic are available.
Power awareness indicates the ability of the system power to scale with changing conditions and quality requirements. Scalability is an important figure-of-merit since it allows the end user to implement operational policy. just like the user of mobile multimedia equipment needs to select between better quality and longer battery operation time.
This dissertation discusses power/energy optimization and performs analysis on both synchronous and asynchronous logic. The major contributions of this dissertation include:
1 ) A 2-Dimensional Pipeline Gating technique for synchronous pipelined circuits to improve their power awareness has been proposed. This technique gates the corresponding clock lines connected to registers in both vertical direction (the data flow direction) and horizontal direction (registers within each pipeline stage) based on current input precision.
2) Two energy reduction techniques, Signal Bypassing & Insertion and Zero Insertion. have been developed for NCL circuits. Both techniques use Nulls to replace redundant Data 0's based on current input precision in order to reduce the switching activity while Signal Bypassing & Insertion is for non-pipelined NCI, circuits and Zero Insertion is for pipelined counterparts. A dynamic active-bit detection scheme is also developed as an expansion.
3) Two energy estimation techniques, Equivalent Inverter Modeling based on Input Mapping in transistor-level and Switching Activity Modeling in gate-level, have been proposed. The former one is for CMOS gates with feedbacks and the latter one is for NCL circuits.
Notes
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Graduation Date
2004
Semester
Spring
Advisor
Yuan, J. S.
Degree
Doctor of Philosophy (Ph.D.)
College
College of Engineering and Computer Science
Department
Electrical and Computer Engineering
Degree Program
Electrical and Computer Engineering
Format
Language
English
Rights
Written permission granted by copyright holder to the University of Central Florida Libraries to digitize and distribute for nonprofit, educational purposes.
Length of Campus-only Access
None
Access Status
Doctoral Dissertation (Open Access)
Identifier
DP0001720
Subjects
Engineering -- Dissertations, Academic; Dissertations, Academic -- Engineering
STARS Citation
Di, Jia, "Energy Aware Design and Analysis for Synchronous and Asynchronous Circuits" (2004). Retrospective Theses and Dissertations. 5102.
https://stars.library.ucf.edu/rtd/5102
Contributor (Linked data)
Yuan, J. S. [VIAF]
Yuan, J. S. [LC]
University of Central Florida. College of Engineering and Computer Science (Q7895235)
University of Central Florida. College of Engineering and Computer Science [VIAF]
University of Central Florida. College of Engineering and Computer Science [LC]
Accessibility Status
Searchable text