Keywords

Neutron counters

Abstract

Neutron bombardment of bipolar transistors creates cluster defects in semiconductor material. The clusters are small volumes of semiconductor material containing several hundred atoms displaced from their proper lattice sites owing to collision processes. They act as recombination centers in transistor bases, reducing minority carrier lifetime and consequently reducing transistor current gain. The damage is permanent to the semiconductor device and can only be corrected by thermally annealing the transistor. Copious test data available on bipolar transistors d.c. gain (hFE) response to incident fast neutron fluences confirm their mathematically derivable functional relationships. This report develops a neutron fluence detector system based upon the current gain (hFE) degradation. An approximate model extending these results to include the effects of temperature is developed. A probe containing an npn silicon planar transistor with associated components to allow hFE measurements is designed. A thermal sensor is also designed. More precise neutron data is obtained by correcting for d.c. current gain versus ambient temperature error. The design of the probe is the major contribution in this report. In addition to the computer simulation of the probe model a system architecture and implementation is presented. The detector system is comprised of the probe and associated data acquisition I/O circuitry. A microcomputer processes the probe data to calculate the neutron fluence received.

Notes

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Graduation Date

1983

Advisor

Martin, Robert J.

Degree

Master of Science (M.S.)

College

College of Engineering

Degree Program

Engineering

Format

PDF

Pages

68 p.

Language

English

Rights

Public Domain

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0014099

Accessibility Status

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