Metal and dielectric film deposition stress to silicon substrate

Keywords

Silicon; Thin films

Abstract

In VLSI device fabrication, multiple layers of films are deposited on silicon wafers to manufacture semiconductor devices. The deposition of these films can create residual film stress due to the factors like Coefficient of Thermal Expansion (CTE) mismatch between the film and underlying substrate and intrinsic stress during growth. The measurement of film stress can detect many problems in advance, such as metal voids, hillocks, silicide lifting and dielectric cracks that result from the film stress. The ability to accurately measure film stress during production, as well as during research and development, enables early correction of problems and increases the reliability and yield of the production process. The accurate measurement of film stress is becoming a necessity, as our technologies advance to sub-micron geometry, wafer diameters increase and the fabrication processes become more complex. Besides the effect on device reliability and yield, this process created film stresses

have big impact on silicon substrate where it causes wafer substrates to deform. The deformation on wafers creates major problems from one processing area to the next where it reduces wafer and device yield. The films are applied to wafers by common techniques such as sputtering or various chemical vapor deposition techniques. The deposition parameters determine the type and level of stress on the wafer. Depending on the type of the stress, wafers might be concaved in (saucer shaped) or out (domed) where it will affect the processing condition at the following processing areas. There have been many studies to address the stress effect of deposited thin films to a wafer. Here are the some of the films and their material property in term of stress factor. Silicon Dioxide (Si02) is naturally compressively strained on silicon. It can be tensile at the absence of water. Poly-silicon can be made both compressive and tensile depending on the deposition parameters. Silicon Nitride (Si3N4) films are highly tensile stressed on silicon, but the stress can be sharply reduced and even turned into compressive stress by incorporating extra silicon. The purpose of this study was not to accomplish another stress experiment, but try o understand the effect of one layer to another. During the course of the study (thesis), the Radius of Curvature (ROC) measurements collected at many steps of the sub-micron process technology to understand the effect of each process to the wafer substrate as well as to understand the effect of these created stress from one level to the next level. The collected data is correlated to the wafer yield upon completion of the routing, which included over 700 steps at 7 level metal interconnects, during the testing to understand its effect to the wafer yield.

Notes

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Graduation Date

2003

Advisor

Sundaram, Kalpathy B.

Degree

Master of Science (M.S.)

College

College of Engineering

Department

Electrical Engineering and Computer Science

Degree Program

Electrical Engineering

Format

PDF

Pages

77 p.

Language

English

Length of Campus-only Access

None

Access Status

Masters Thesis (Open Access)

Identifier

DP0029105

Subjects

Dissertations, Academic -- Engineering; Engineering -- Dissertations, Academic

Accessibility Status

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