Title

Vlsi Design Of Processing Element For Reconfigurable Systolic Architectures Based On Lns.

Abstract

The design and development of a processing element (PE) in an orthogonal systolic architecture, using the state of the art in VLSI technology, is presented. The goal was to create a high-speed, high-precision PE which would be adaptive to a highly configurable systolic architecture. In order to achieve the necessary computational throughput, the arithmetic unit of the PE was implemented using the logarithmic number system. The PE is designed to take full advantage of parallel communications, both internally and externally.

Publication Date

1-1-1988

Publication Title

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Number of Pages

2080-2083

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

0023708901 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0023708901

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