Title

Array Noise Analysis For High-Density Dynamic Ram Design

Abstract

The analytical modeling of the bit line noise analysis for different DRAM architectures has been developed. The analytical expressions provide insight into the charge redistribution when the word lines turn on. The topology for array noise extraction in SPICE circuit simulation is presented. The SPICE simulations show good agreement with analytical results.

Publication Date

12-1-1991

Publication Title

Midwest Symposium on Circuits and Systems

Volume

2

Number of Pages

649-652

Document Type

Article; Proceedings Paper

Identifier

scopus

Personal Identifier

scopus

Socpus ID

0026406442 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0026406442

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