Title
Impact of technology on low-voltage CMOS and BiCMOS switching delay
Abstract
An alternative switching delay reduction technique for CMOS & BiCMOS digital circuits is examined. A simplified BSIM3V2 model equation is used to analyze CMOS inverter delay for different VDD, Tox, and VT. PSPICE BiCMOS delay results are presented over a wide range of VDD, Tox, and VT.
Publication Date
1-1-1998
Publication Title
Conference Proceedings - IEEE SOUTHEASTCON
Number of Pages
170-173
Document Type
Article; Proceedings Paper
Personal Identifier
scopus
Copyright Status
Unknown
Socpus ID
0031681941 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/0031681941
STARS Citation
Davis, Kelly L. and Yuan, J. S., "Impact of technology on low-voltage CMOS and BiCMOS switching delay" (1998). Scopus Export 1990s. 3403.
https://stars.library.ucf.edu/scopus1990/3403
COinS