Title

Testing The Impact Of Process Defects On Ecl Powerdelay Performance

Abstract

The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evaluated. We have developed modelling equations including process defects in the delay analysis. The delay equation provides an insight into the sensitivity of various process defects on the ECL gate delay. The testing model equations are physics-based and can be generalized to digital circuits other than ECL. © 1993 Taylor & Francis Ltd.

Publication Date

1-1-1993

Publication Title

International Journal of Electronics

Volume

74

Issue

2

Number of Pages

201-207

Document Type

Article

Identifier

scopus

Personal Identifier

scopus

DOI Link

https://doi.org/10.1080/00207219308925826

Socpus ID

0027544213 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0027544213

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