Title

Array Noise Analysis For Multi-Megabit Dram Design

Abstract

An analytical model for bit-line coupling noise in various DRAM architectures has been developed. The analytical expressions developed provide insight into the charge redistribution when the word lines turn on. They are also useful for determining the noise-to-signal ratio and for designing the sense amplifier circuit. Noise extracted from SPICE circuit simulation is included and is compared against the results from the present analytical model. Good agreement is found. © 1993 Taylor & Francis Ltd.

Publication Date

1-1-1993

Publication Title

International Journal of Electronics

Volume

74

Issue

2

Number of Pages

265-279

Document Type

Article

Identifier

scopus

Personal Identifier

scopus

DOI Link

https://doi.org/10.1080/00207219308925833

Socpus ID

0027541784 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0027541784

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