Title

Spice Modeling And Quick Estimation Of Mosfet Mismatch Based On Bsim3 Model And Parametric Tests

Keywords

Analog circuits; BSIM3v3 model; Statistical circuit simulation; Transistor mismatch

Abstract

This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSIM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared.

Publication Date

10-1-2001

Publication Title

IEEE Journal of Solid-State Circuits

Volume

36

Issue

10

Number of Pages

1592-1595

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/4.953490

Socpus ID

0035472654 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0035472654

This document is currently not available here.

Share

COinS