Title

Supply Voltage Scalable System Design Using Self-Timed Circuits

Keywords

Circuits; Computer architecture; Costs; Delay; Digital signal processing; Power system reliability; Scalability; Signal processing; Very large scale integration; Voltage

Abstract

Supply voltage scalable system design for low power is investigated using self-timed circuits in this paper. Two architectures are proposed to achieve supply voltage scalability, for preserved quality and energy-quality tradeoff respectively, In the first architecture, the supply-voltage automatically tracks the input data rate of the data path so that the supply-voltage can be kept as small as possible while maintaining the speed requirement and processing quality. In the second one, further energy saving is achieved at the cost of signal-noise-ratio loss in digital signal processing when an ultra-low supply voltage is applied. Cadence simulation shows the effectiveness for both architectures. More than 40% to 70% power can be saved by introducing -150 to -10 dB error in a case study: speech signal processing.

Publication Date

1-1-2003

Publication Title

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volume

2003-January

Number of Pages

161-166

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2003.1183368

Socpus ID

67651103179 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/67651103179

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