Title

Enhanced Techniques For Current Balanced Logic In Mixed-Signal Ics

Keywords

Analytical models; Circuit analysis; Circuit noise; Circuit simulation; Delay; Logic design; Negative feedback; Noise reduction; Power dissipation; SPICE

Abstract

In this paper, dual-VT and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-VT technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.

Publication Date

1-1-2003

Publication Title

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volume

2003-January

Number of Pages

278-279

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2003.1183499

Socpus ID

5044241909 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/5044241909

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