Title

Design Of Enhancement Current-Balanced Logic For Mixed-Signal Ics

Abstract

The dual-Vτ and negative feedback mechanisms have been proposed to enhance Current Balanced Logic for low noise IC design. The detailed circuit analysis and SPICE simulations show that the dual-Vτ structure has advantages over the conventional CBL design in many design aspects, such as gate area, delay, power dissipation, and switching noise. The negative feedback can further reduce the current spike with some tradeoffs. The design procedures of the enhancement CBL are discussed in detail. The proposed methods give the designer a better control of the current spike for mixed-signal integrated circuits.

Publication Date

7-15-2003

Publication Title

Proceedings - IEEE International Symposium on Circuits and Systems

Volume

1

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

0038790052 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0038790052

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