Title

Soft Digital Signal Processing Using Self-Timed Circuits

Abstract

In this paper, we propose a self-timed architecture for low power digital signal processing with ultra-low supply voltage. Compared to synchronous circuits, self-timed circuits are more robust at very low voltage. In many signal-noise-ratio (SNR)-required digital signal processing applications, this robustness allows the circuit to operate with very low supply voltage, even if some data samples are missed due to this low voltage. The missing leads to an SNR degradation. The degradation depends on input data frequency, supply voltage, specific circuit architecture, and process technology. Simulation' shows that more than 40% to 70% power can be saved by introducing -15dB to -10 dB error in a case study: speech signal processing. © 2002 IEEE.

Publication Date

12-1-2002

Publication Title

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

Number of Pages

194-198

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

84864686117 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/84864686117

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