Title

Low Power Operation Using Self-Timed Circuits And Ultra-Low Supply Voltage

Keywords

Adders; Circuit simulation; Degradation; Delay; Digital signal processing; Low voltage; Registers; Robustness; Signal processing; Speech processing

Abstract

In this paper, a self-timed architecture for low voltage low power design is proposed. Compared to synchronous circuits, self-timed circuits are more robust to ultra-low supply voltage. In many signal-noise-ratio (SNR)-required DSP applications, this robustness allows the circuit to operate with very low supply voltage, even if some data samples are missed due to this low voltage. These missed data are interpolated at the output. Simulation shows that a significant power saving can be achieved at an acceptable SNR loss in a case study - speech signal processing. This proposed low power method can be combined with many other low power schemes at various levels to achieve further power saving.

Publication Date

1-1-2002

Publication Title

Proceedings of the International Conference on Microelectronics, ICM

Volume

2002-January

Number of Pages

185-188

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ICM-02.2002.1161526

Socpus ID

47349115057 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/47349115057

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