Title

Statistical Modeling Of Mos Devices For Parametric Yield Prediction

Abstract

In the manufacturing of VLSI circuits, engineering designs should take into consideration random variations arising from processing. In this paper, statistical modeling of MOS devices is reviewed, and effective and practical models are developed to predict the performance spread (i.e., parametric yield) of MOS devices and circuits due to the process variations. To illustrate their applications, the models are applied to the 0.25 μm CMOS technology, and measured data are included in support of the model calculations. © 2002 Elsevier Science Ltd. All rights reserved.

Publication Date

1-1-2002

Publication Title

Microelectronics Reliability

Volume

42

Issue

4-5

Number of Pages

787-795

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/S0026-2714(01)00262-1

Socpus ID

0036540087 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0036540087

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