Title

3D-Mesh Interconnect Architecture For Network Processors

Abstract

In this paper, we present a 3D-mesh architecture which is utilized as a processor-memory interconnection system to increase the throughput of memory system currently used on line cards. The 3D-mesh architecture is integrated on the line card to allow communication among multiple processing elements to multiple shared memories. The 3D-mesh provides many desirable performance qualities such as low latency, off-chip scalability, and most important higher memory bandwidth than its counterpart - the single shared-bus.

Publication Date

12-1-2005

Publication Title

Proceedings of the 2005 International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA'05

Volume

2

Number of Pages

521-525

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

Socpus ID

60749134690 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/60749134690

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