Title

A Spice-Like Reliability Model For Deep-Submicron Cmos Technology

Keywords

Hot-carrier stress; MOS devices; Reliability

Abstract

Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and good agreements between the measured and simulated results have been obtained for devices fabricated from the 0.18-μm CMOS technology. © 2005 Elsevier Ltd. All rights reserved.

Publication Date

10-1-2005

Publication Title

Solid-State Electronics

Volume

49

Issue

10

Number of Pages

1702-1707

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.sse.2005.09.003

Socpus ID

27744528278 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/27744528278

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