Title

A Compact Model For Reliability Simulation Of Deep-Submicron Mos Devices And Circuits

Abstract

Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and measured data obtained from devices fabricated from the 0.18-μm CMOS technology have been included in support of the model development. © 2005 IEEE.

Publication Date

1-1-2005

Publication Title

2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

Number of Pages

391-396

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/EDSSC.2005.1635289

Socpus ID

43549091797 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/43549091797

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