Title

Substrate Current, Gate Current And Lifetime Prediction Of Deep-Submicron Nmos Devices

Keywords

Gate current; Lifetime model; MOS devices; Reliability; Substrate current

Abstract

Experimental results are presented to indicate that the widely used power-law models for lifetime estimation are questionable for deep-submicron (<0.25 μm) MOS devices, particularly for the case of large substrate current stressing. This observation is attributed to the presence of current components, such as the gate tunneling current and base current of parasitic bipolar transistor, that do not induce device degradation. A more effective extrapolation method is proposed as an alternative for the reliability characterization of deep-submicron MOS devices. © 2004 Elsevier Ltd. All rights reserved.

Publication Date

3-1-2005

Publication Title

Solid-State Electronics

Volume

49

Issue

3

Number of Pages

505-511

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.sse.2004.11.020

Socpus ID

12344316337 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/12344316337

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