Title

A Reconfigurable Memory Management Core For Java Applications

Abstract

Shortly after the introduction of Java technology, numerous research efforts went into overcoming the performance shortcomings of the Java Virtual Machine (JVM) by mapping it onto hardware. It seems that most works addressing the implementation of a JVM in hardware often excludes the mapping of compute-intensive tasks such as memory allocation, garbage collection, and exception handling. In this paper, we propose a hardware architecture to support dynamic memory allocation and deallocation operations in a JVM. Such hardware architectures are becoming attractive alternatives when compared to their software implementation counterparts. This architecture, called Memory Management Core (MMC), (i) supports a memory map that is independent of the physical memory size, (ii) allocates blocks with exact size to minimize fragmentation, (iii) performs in-place coalescing and splitting of the memory blocks, (iv) services concurrent multiple allocation and de-allocation requests to achieve maximum performance, and (iv) attempts to achieve a high utilization of all its hardware components. A prototype of this architecture is implemented and mapped on a suitable FPGA device to analyze its performance. The obtained results show that the FPGA implementation of this architecture can service memory allocation and deallocation many order of magnitude faster than software implementations for memory-intensive applications.

Publication Date

9-24-2004

Publication Title

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Number of Pages

309-312

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/ISVLSI.2004.1339568

Socpus ID

4544383753 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/4544383753

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