Title

Modeling Of Direct Tunneling And Surface Roughness Effects On C-V Characteristics Of Ultra-Thin Gate Mos Capacitors

Abstract

Effects of direct tunneling and surface roughness on the capacitance-voltage characteristics of ultra-thin gate deep submicron MOS transistors have been studied. An improved equivalent circuit model to account for surface roughness and direct tunneling on the ultra-thin gate MOS capacitors in a unified manner is proposed. The capacitance subject to direct tunneling and surface roughness effect is smaller than that without surface roughness effect.

Publication Date

1-1-2001

Publication Title

Solid-State Electronics

Volume

45

Issue

2

Number of Pages

373-377

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/S0038-1101(00)00234-3

Socpus ID

0035247096 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/0035247096

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