Title
Design Optimization Of Stacked Layer Dielectrics For Minimum Gate Leakage Currents
Abstract
An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I-V curves are observed for Si3N4/SiO2, Ta2O5/SiO2, Ta2O5/SiO2-yNy, Ta2O5/Si3N4, and TiO2/SiO2 stacked gates except for Al2O3/SiO2 structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.
Publication Date
12-1-2000
Publication Title
Solid-State Electronics
Volume
44
Issue
12
Number of Pages
2165-2170
Document Type
Article
Personal Identifier
scopus
DOI Link
https://doi.org/10.1016/S0038-1101(00)00185-4
Copyright Status
Unknown
Socpus ID
0034506413 (Scopus)
Source API URL
https://api.elsevier.com/content/abstract/scopus_id/0034506413
STARS Citation
Zhang, J.; Yuan, J. S.; and Ma, Y., "Design Optimization Of Stacked Layer Dielectrics For Minimum Gate Leakage Currents" (2000). Scopus Export 2000s. 708.
https://stars.library.ucf.edu/scopus2000/708