Title

Dynamic Voltage Stress Effects On Nmos Varactor

Abstract

The degradations in the nMOS device due to high-frequency (900 MHz) dynamic stress are shown experimentally. The stress-induced shifts in DC and larger-signal C-V characteristics are presented. Although the high-frequency stress-induced degradations are much smaller than DC stress, the effects on C-V curves and quality factor cannot be neglected. An nMOS LC oscillator, wherein the varactor is operated under the same dynamic bias conditions as in the stress experiment, has been evaluated through Cadence Spectre simulation. The performance of the LC oscillator degrades significantly due to the dynamic stress. © 2006.

Publication Date

9-1-2006

Publication Title

Microelectronics Reliability

Volume

46

Issue

9-11

Number of Pages

1812-1816

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.microrel.2006.07.075

Socpus ID

33747790871 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/33747790871

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