Title

A New Model For Four-Terminal Junction Field-Effect Transistors

Keywords

Analog circuit; Compact modeling; Field effect transistors

Abstract

This paper presents a compact and semi-empirical model for a four-terminal (independent top and bottom gates) junction field-effect transistor (JFET). The model describes the steady-state characteristics for all bias conditions with a unified equation. Moreover, the model provides a high degree of accuracy and continuity for the different operation regions, a critical factor for robust analog circuit simulations. Capacitance modeling is also included to describe the JFET small-signal behavior. The model has been implemented in Cadence framework via Verilog-A and compared with data measured from JFETs used at Texas Instruments. © 2006 Elsevier Ltd. All rights reserved.

Publication Date

3-1-2006

Publication Title

Solid-State Electronics

Volume

50

Issue

3

Number of Pages

422-428

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.sse.2006.01.001

Socpus ID

33646095768 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/33646095768

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