Title

A High Throughput 3D-Bus Interconnect For Network Processors

Keywords

Interconnect systems; k-ary n-cube networks; Line cards; Memory management; Network processors

Abstract

Deep layer processing and increasing line rates present a memory challenge to processor-memory communications located on network line cards. In this paper, we introduce a packet-based, off-chip interconnect to increase the throughput of memory system currently used on line cards. The 3D-bus architecture allows multiple packet processing elements on a line card to access multiple memory modules. Our network-on-board includes a routing protocol as well as a node switching mechanism to minimize packet congestion and packet loss. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition. Performance results show that our interconnect significantly outperforms its competitors, such as shared-bus, PCI Express, infiniband and HyperTransport, reaching peak throughput beyond 400 Gbps. Moreover, it provides other high performance qualities including low latency, off-chip scalability, low transmission failure-rate and high memory bandwidth. © 2005 Elsevier B.V. All rights reserved.

Publication Date

2-1-2006

Publication Title

Microprocessors and Microsystems

Volume

30

Issue

1

Number of Pages

15-25

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1016/j.micpro.2005.04.002

Socpus ID

31344442065 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/31344442065

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