Title

Performance Evaluation Of Wormhole Routed Network Processor-Memory Interconnects

Abstract

Network line, cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processor-memory environments, to create data transfer bottle-necks and hot-spots. Solutions to the memory bandwidth bottleneck are limited by the area available on the line card and network processor I/O pins. As a result, we propose to explore more suitable off-chip interconnect and communication mechanisms that will replace the existing systems and that will provide extraordinary high throughput. We utilize our customdesigned, event-driven, interconnect simulator to evaluate the performance of wormhole routed packet-based off-chip k-ary n-cube interconnect architectures for line cards. Our performance results show that wormhole routed k-ary n-cube based interconnect topologies significantly outperform the existing line card interconnects and they are able to sustain higher traffic loads. © 2006 IEEE.

Publication Date

1-1-2006

Publication Title

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volume

2006

Number of Pages

-

Document Type

Article; Proceedings Paper

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/IPDPS.2006.1639641

Socpus ID

33847112555 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/33847112555

This document is currently not available here.

Share

COinS