Title

Design Of Asynchronous Circuits For High Soft Error Tolerance In Deep Submicrometer Cmos Circuits

Keywords

Asynchronous circuit; Null convention logic (NCL); Soft error

Abstract

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented. © 2009 IEEE.

Publication Date

3-1-2010

Publication Title

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volume

18

Issue

3

Number of Pages

410-422

Document Type

Article

Personal Identifier

scopus

DOI Link

https://doi.org/10.1109/TVLSI.2008.2011554

Socpus ID

77649183496 (Scopus)

Source API URL

https://api.elsevier.com/content/abstract/scopus_id/77649183496

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